Abstract
We demonstrate a 2 × 2 silicon-plasmonic router architecture with 320
Gb/s throughput capabilities for optical interconnect applications. The proposed router
platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP)
2 × 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic
motherboard that is responsible for traffic multiplexing and header processing
functionalities. We present experimental results of a Poly-methyl-methacrylate
(PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two racetrack
resonators of 5.5 $\mu$m radius and 4 $\mu$m-long straight sections and operates as a
passive add/drop filtering element. We derive its frequency-domain transfer function,
confirm its add/drop experimental spectral response, and proceed to a circuit-level
model for dual-ring DLSPP designs supporting 2 × 2 thermo-optic switch
operation. The validity of our circuit-level modeled 2 × 2 thermo-optic switch
is verified by means of respective full vectorial three-dimensional Finite Element
Method (3D-FEM) simulations. The router setup is completed by means of two 4 × 1
SOI multiplexing circuits, each one employing four cascaded second order micro-ring
configurations with 100 GHz spaced resonances. Successful interconnection between the
DLSPP switching matrix and the SOI circuitry is performed through a butt-coupling design
that, as shown via 3D-FEM analysis, allows for small coupling losses of as low as 2.6
dB. The final router architecture is evaluated through a co-operative simulation
environment, demonstrating successful 2 × 2 routing for two incoming
4-wavelength Non-Return-to-Zero (NRZ) optical packet streams with 40 Gb/s
line-rates.
© 2011 IEEE
PDF Article
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