Abstract
We report here on the design, fabrication, and high-speed performance
of a parallel optical transceiver based on a single CMOS amplifier chip incorporating
16 transmitter and 16 receiver channels. The optical interfaces to the chip
are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly
flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD
arrays operate at 985 nm and include integrated lenses. The complete transceivers
are low-cost, low-profile, highly integrated assemblies that are compatible
with conventional chip packaging technology such as direct flip-chip soldering
to organic circuit boards. In addition, the packaging approach, dense hybrid
integration, readily scales to higher channel counts, supporting future massively
parallel optical data buses. All transmitter and receiver channels operate
at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240Gb/s.
Interchannel crosstalk was extensively characterized and the dominant source
was found to be between receiver channels, with a maximum sensitivity penalty
of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by
active aggressor channels. The transceiver measures 3.25$\, \times\,$5.25 mm
and consumes 2.15 W of power with all channels fully operational. The per-bit
power consumption is as low as 9 mW/Gb/s, and this is the first single-chip
optical transceiver capable of channel rates in excess of 10 Gb/s. The area
efficiency of 14 Gb/s/mm$^{2}$ per link is the highest ever reported for any parallel
optical transmitter, receiver, or transceiver reported to-date.
© 2009 IEEE
PDF Article
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